View ISL6263C_4920706.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL6263C
Data Sheet July 8, 2010 FN6745.1
5-Bit VID Single-Phase Voltage Regulator with Current Monitor for GPU Core Power
The ISL6263C IC is a Single-Phase Synchronous-Buck PWM voltage regulator for GPU core power application. It features Intersil's Robust Ripple Regulator (R3) TechnologyTM. Integrated current monitor, differential remote sense amplifier, MOSFET driver and bootstrap diode result in smaller implementation area and lower component cost. Intersil's R3 TechnologyTM combines the best features of both fixed-frequency PWM and hysteretic PWM, delivering excellent light-load efficiency and superior load transient response by commanding variable switching frequency during the transitory event. For maximum conversion efficiency, the ISL6263C automatically enters diode emulation mode (DEM) when the inductor current attempts to flow negative. DEM is highly configurable and easy to set-up. A PWM filter can be enabled, which prevents the switching frequency from entering the audible spectrum as a result of extremely light load while in DEM. The GPU core voltage can be dynamically programmed from 0.41200V to 1.28750V by the five VID input pins without requiring sequential stepping of the VID states. The ISL6263C requires only one capacitor for both the soft-start slew-rate and the dynamic VID slew-rate by internally connecting the SOFT pin to the appropriate current source. The voltage Kelvin sensing is accomplished with an integrated unity-gain true differential amplifier.
Features
* Precise Single-Phase Core Voltage Regulator - 0.5% System Accuracy 0C to +100C - Differential Remote GPU Die Voltage Sense * Real-Time GPU Current Monitor Output * Applications up to 25A * Input Voltage Range: +5.0V to +25.0V * Programmable PWM Frequency: 200kHz to 500kHz * Pre-Biased Output Start-Up Capability * 5-Bit Voltage Identification Input (VID) - 0.41200V to 1.28750V - 25.75mV Steps - Sequential or Non-Sequential VID Change On-the-Fly * Configurable PWM Modes - Forced Continuous Conduction Mode - Automatic Entry and Exit of Diode Emulation Mode - Selectable Audible Frequency PWM Filter * Integrated MOSFET Drivers and Bootstrap Diode * Choice of Current Sense Schemes - Lossless Inductor DCR Current Sense - Precise Resistive Current Sense * Overvoltage, Undervoltage and Overcurrent Protection * Pb-Free (RoHS Compliant)
Ordering Information
PART NUMBER (Notes 2, 3) ISL6263CHRZ PART MARKING TEMP RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
Pinout
PGOOD
ISL6263C (32 LD 5x5 QFN) TOP VIEW
VR_ON AF_EN IMON VID3 26 VID2 25 24 VID1 23 VID0 22 PVCC THERMAL PAD (BOTTOM) 21 LGATE 20 PGND 19 PHASE 18 UGATE 17 BOOT 9 RTN 10 ICOMP 11 ISN 12 VO 13 ISP 14 VIN 15 VSS 16 VDD VID4 27 FDE 32
ISL6263 CHRZ -10 to +100 32 Ld 5x5 QFN L32.5x5
ISL6263CHRZ-T ISL6263 CHRZ -10 to +100 32 Ld 5x5 QFN L32.5x5 (Note 1) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6263C. For more information on MSL please see techbrief TB363.
RBIAS SOFT OCSET VW COMP FB VDIFF VSEN 1 2 3 4 5 6 7 8
31
30
29
28
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved. R3 TechnologyTM is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
Block Diagram
VR_ON VDD + - VSS 1:1 VREF 1.545V PWM CONTROL DIODE EMULATION AUDIBLE FREQUENCY FILTER SEVERE OVERVOLTAGE SOFT CROWBAR CONTROL PHASE SHOOT-THROUGH PROTECTION PVCC PGOOD BOOT
POR VREF x2 - SCP + PGOOD SHORT CIRCUIT OVERCURRENT UNDERVOLTAGE
DRIVER
UGATE
VID1 VID2 VID3 VID4 VID DAC ISS IDVID + - + E/A -
2
RBIAS OCSET ISP ISN ICOMP VO + - + - - OCP + VSEN RTN VDIFF + - VID0 SOFT
FN6745.1 July 8, 2010
OVERVOLTAGE FAULT LATCH
DRIVER
LGATE
PGND X31 FDE AF_EN VW + - VW 20% VW 30% gmVIN PWM
ISL6263C
VW
R3 MODULATOR
gmVsoft VCOMP
FB
COMP
IMON
VIN
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF THE ISL6263C
ISL6263C Simplified Application Circuit for DCR Current Sense
RVDD V5V CVDD VDD RRBIAS RBIAS CSOFT SOFT UGATE BOOT RIMON PGOOD IMON CIMON PHASE CBOOT LOUT VOUT QHS CIN VIN VIN PVCC CPVCC
VID<0:4> VR_ON AF_EN FDE VOUT VGND VSEN RTN VW ISP LGATE PGND
QLS
COUT
RS RNTC
ISL6263C
RFSET CFSET VO CN RP RNTCS
CCOMP1 ROCSET COMP RCOMP CCOMP2 FB OCSET ISN RIS1
VDIFF RDIFF2 CDIFF VSS RDIFF1 RGND 0 ICOMP
RIS2
CIS
FIGURE 2. ISL6263C GPU CORE VOLTAGE REGULATOR SOLUTION WITH DCR CURRENT SENSE
3
FN6745.1 July 8, 2010
ISL6263C Simplified Application Circuit for Resistive Current Sense
RVDD V5V CVDD VDD RRBIAS RBIAS CSOFT SOFT UGATE BOOT RIMON PGOOD IMON CIMON PHASE CBOOT LOUT RSNS VOUT QHS CIN VIN VIN PVCC CPVCC
VID<0:4> VR_ON AF_EN FDE VOUT VGND VSEN RTN VW ISP LGATE PGND
QLS
COUT
RS
ISL6263C
RFSET CFSET VO CN
CCOMP1 ROCSET COMP RCOMP CCOMP2 FB OCSET ISN RIS1
VDIFF RDIFF2 CDIFF VSS RDIFF1 RGND 0 ICOMP
RIS2
CIS
FIGURE 3. ISL6263C GPU CORE VOLTAGE REGULATOR SOLUTION WITH RESISTOR CURRENT SENSE
4
FN6745.1 July 8, 2010
ISL6263C
Absolute Voltage Ratings
VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V VSS to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V PHASE to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V (<100ns Pulse Width, 10J) -5.0V BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V BOOT to VSS or PGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V UGATE. . . . . . . . . . . . . . . . . . . (DC) -0.3V to PHASE, BOOT +0.3V (<200ns Pulse Width, 20J) -4.0V LGATE . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to PGND, PVCC +0.3V (<100ns Pulse Width, 4J) -2.0V ALL Other Pins. . . . . . . . . . . . . . . . . . . . . -0.3V to VSS, VDD +0.3V
Thermal Information
Thermal Resistance (Typical, Notes 4, 5) JA (C/W) JC (C/W) 32 Ld QFN Package. . . . . . . . . . . . . . . 35 6 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150C Operating Temperature Range . . . . . . . . . . . . . . . .-10C to +100C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . -10C to +100C VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +25V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% FDE to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
These specifications apply for TA = -10C to +100C, unless otherwise stated. All typical specifications TA = +25C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range, -10C to +100C. SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS
PARAMETER VIN VIN Input Resistance VIN Shutdown Current VDD and PVCC VDD Input Bias Current VDD Shutdown Current VDD POR THRESHOLD Rising VDD POR Threshold Voltage Falling VDD POR Threshold Voltage REGULATION Output Voltage Range
R VIN IVIN_SHDN
VR_ON = 3.3V VR_ON = 0V, VIN = 25V
1.0 1.0
M A
IVDD IVDD_SHDN V
VR_ON = 3.3V VR_ON = 0V, VDD = 5.0V
2.7
3.3 1.0
mA A
VDD_THR VDD_THF
4.35 3.85 4.10
4.50
V V
V
V
OUT_MAX OUT_MIN
VID<4:0> = 00000 VID<4:0> = 11111 VID<4:0> = 00000 to 11110 (1.28750V to 0.51500V) VID<4:0> = 11110 to 11111 (0.51500V to 0.41200V)
1.28750 0.41200 25.75 103 -0.5 -1.0 -3.0 0.5 1.0 3.0
V V mV/step mV % % %
V VID Voltage Step
System Accuracy
VID = 1.28750V to 0.74675V TA = 0C to +100C VID = 0.72100V to 0.51500V TA = 0C to +100C VID = 0.41200 TA = 0C to +100C
5
FN6745.1 July 8, 2010
ISL6263C
Electrical Specifications
These specifications apply for TA = -10C to +100C, unless otherwise stated. All typical specifications TA = +25C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range, -10C to +100C. (Continued) SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS
PARAMETER PWM Nominal Frequency Frequency Range Audio Filter Frequency AMPLIFIERS Error Amplifier DC Gain (Note 7) Error Amplifier Gain-Bandwidth Product (Note 3) Error Amp Slew Rate (Note 7) FB Input Bias Current Current Sense Amplifier Offset RBIAS Voltage SOFT-START CURRENT Soft-Start Current Soft Dynamic VID Current CURRENT MONITOR Current Monitor Output Voltage Range V
f
SW
RFSET = 7kVCOMP = 2V
318 200
333
348 500
kHz kHz kHz
f
AF
28
AV0 GBW SR IFB
ISENSE_OFS
90 CL = 20pF CL = 20pF VFB = 1.28750V -0.3 R
RBIAS = 150k
dB MHz V/s 150 0.3 nA mV V
18 5 10
V
RBIAS
1.495
1.515
1.535
ISS IDVID V |SOFT - REF|>100mV
-47 180
-42 205
-37 230
A A
IMON
V V
V ICOMP - O = 40mV V ICOMP - O = 10mV
1.22 0.285 3.1 VIMON/ 250
1.24 0.310 3.4 VIMON/ 180
1.26 0.335
V V V
Current Monitor Maximum Output Voltage Current Monitor Maximum Current Sinking Capability Current Monitor Sourcing Current Current Monitor Sinking Current Current Monitor Impedance (Note 7) GATE DRIVER UGATE Source Resistance (Note 7) UGATE Source Current (Note 7) UGATE Sink Resistance (Note 7) UGATE Sink Current (Note 7) LGATE Source Resistance (Note 7) LGATE Source Current (Note 7) LGATE Sink Resistance (Note 7) LGATE Sink Current (Note 7) UGATE Pull-Down Resistor UGATE Turn-On Propagation Delay LGATE Turn-On Propagation Delay BOOTSTRAP DIODE Forward Voltage Reverse Leakage
V
IMONMAX
VIMON/ 130
A mA mA
ISC_IMON ISK_IMON
V V
V ICOMP - O = 40mV V ICOMP - O = 40mV
2.0 2.0 7
IIMON ISK_IMON, IIMON ISC_IMON
RUGSRC IUGSRC RUGSNK IUGSNK RLGSRC ILGSRC RLGSNK ILGSNK RPD tPDRU tPDRL
500mA Source Current VUGATE_PHASE = 2.5V 500mA Sink Current VUGATE_PHASE = 2.5V 500mA Source Current VLGATE_PGND = 2.5V 500mA Sink Current VLGATE_PGND = 2.5V
1.0 2.0 1.0 2.0 1.0 2.0 0.5 4.0 1.1
1.5
A
1.5
A
1.5
A
0.9
A k
PVCC = 5V, UGATE open PVCC = 5V, LGATE open
20 7
30 15
44 30
ns ns
VF IR
PVCC = 5V, IF = 10mA VR = 16V
0.56
0.69
0.76 5.0
V A
6
FN6745.1 July 8, 2010
ISL6263C
Electrical Specifications
These specifications apply for TA = -10C to +100C, unless otherwise stated. All typical specifications TA = +25C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range, -10C to +100C. (Continued) SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS
PARAMETER
POWER GOOD and PROTECTION MONITOR PGOOD Low Voltage PGOOD Leakage Current Overvoltage Threshold (VO-VSOFT) Severe Overvoltage Threshold OCSET Reference Current OCSET Voltage Threshold Offset Undervoltage Threshold (VSOFT-VO) CONTROL INPUTS VR_ON Input Low VR_ON Input High AF_EN Input Low AF_EN Input High VR_ON Leakage VVR_ONL VVR_ONH VAF_ENL VAF_ENH IVR_ONL IVR_ONH AF_EN Leakage IAF_ENL IAF_ENH VID<4:0> Input Low VID<4:0> Input High FDE Input Low FDE Input High VID<4:0> Leakage VVIDL VVIDH VFDEL VFDEH IVIDL IVIDH FDE Leakage IFDEL IFDEH NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Limits established by characterization and are not production tested. VVID = 0V VVID = 1.0V VFDE = 0V VFDE = 1.0V -1.0 0.7 -1.0 0 0.45 0 0.45 1.0 1.0 0.7 0.3 VVR_ON = 0V VVR_ON = 3.3V VAF_EN = 0V VAF_EN = 3.3V -1.0 2.3 -1.0 0 0 0 0.45 1.0 0.4 1.0 2.3 1 1 V V V V A A A A V V V V A A A A VPGOOD IPGOOD VOVP VOVPS IOCSET IPGOOD = 4mA VPGOOD = 3.3V VO rising above VSOFT > 1ms VO rising above 1.55V reference > 0.5s RRBIAS = 150k -1.0 155 1.525 9.9 -3 -360 -300 195 1.550 10.1 0.11 0.40 1.0 235 1.575 10.3 3 -240 V A mV V A mV mV
VOCSET_OFS VICOMP rising above VOCSET > 120s VUVF VO falling below VSOFT for > 1ms
7
FN6745.1 July 8, 2010
ISL6263C Functional Pin Descriptions
RBIAS (Pin 1) - Sets the internal 10A current reference. Connect a 150k 1% resistor from RBIAS to VSS. SOFT (Pin 2) - Sets the output voltage slew-rate. Connect an X5R or X7R ceramic capacitor from SOFT to VSS. The SOFT pin is the non-inverting input of the error amplifier. OCSET (Pin 3) - Sets the overcurrent threshold. Connect a resistor from OCSET to VO. VW (Pin 4) - Sets the static PWM switching frequency in continuous conduction mode. Connect a resistor from VW to COMP. COMP (Pin 5) - Connects to the output of the control loop error amplifier. FB (Pin 6) - Connects to the inverting input of the control loop error amplifier. VDIFF (Pin 7) - Connects to the output of the VDIFF differential amplifier. Together with the FB pin, it is used for the output voltage feedback. VSEN (Pin 8) - This is the VOUT input of the GPU processor Kelvin connection. Connects internally to the non-inverting inputs of the VDIFF differential amplifier. RTN (Pin 9) - This is the VGND input of the GPU processor Kelvin connection. Connects internally to the inverting inputs of the VDIFF differential amplifier. ICOMP (Pin 10) - Connects to the output of the differential current sense amplifier and to the non-inverting inputs of the overcurrent comparator. Used for output current monitor and overcurrent protection. ISN (Pin 11) - This is the feedback of the current sense amplifier. Connects internally to the inverting input of the current sense amplifier. Used for output current sense. VO (Pin 12) - Connects to the inverting inputs of the VDIFF differential amplifier. ISP (Pin 13) - Connects to the non-inverting input of the current sense amplifier. Used for output current sense. VIN (Pin 14) - Connects to the R3 PWM modulator providing input voltage feed-forward. For optimum input voltage transient response, connect near the drain of the high-side MOSFETs. VSS (Pin 15) - Analog ground. VDD (Pin 16) - Input power supply for the IC. Connect to +5VDC and decouple with at least a 1F MLCC capacitor from the VDD pin to the VSS pin. BOOT (Pin 17) - Input power supply for the high-side MOSFET gate driver. Connect an MLCC bootstrap capacitor from the BOOT pin to the PHASE pin. UGATE (Pin 18) - High-side MOSFET gate driver output. Connect to the gate of the high-side MOSFET. PHASE (Pin 19) - Current return path for the UGATE high-side MOSFET gate driver. Detects the polarity of the PHASE node voltage for diode emulation. Connect the PHASE pin to the drains of the low-side MOSFETs. PGND (Pin 20) - Current return path for the LGATE low-side MOSFET gate driver. The PGND pin only conducts current when LGATE pulls down. Connect the PGND pin to the sources of the low-side MOSFETs. LGATE (Pin 21) - Low-side MOSFET gate driver output. Connect to the gate of the low-side MOSFET. PVCC (Pin 22) - Input power supply for the low-side MOSFET gate driver, and the high-side MOSFET gate driver, via the internal bootstrap diode connected between the PVCC and BOOT pins. Connect to +5VDC and decouple with at least 1F of an MLCC capacitor from the PVCC pin to the PGND pin. VID0:VID4 (Pin 23:Pin 27) - Voltage identification inputs. VID0 input is the least significant bit (LSB) and VID4 input is the most significant bit (MSB). IMON (Pin 28) - A voltage signal proportional to the output current of the converter. VR_ON (Pin 29) - A high logic signal on this pin enables the converter and a low logic signal disables the converter. AF_EN (Pin 30) - Used in conjunction with VID0:VID4 and FDE pins to program the diode-emulation and audio filter behavior. Refer to Table 2. PGOOD (Pin 31) - The PGOOD pin is an open-drain output that indicates when the converter is able to supply regulated voltage. Connect the PGOOD pin to a maximum of 5V through a pull-up resistor. FDE (Pin 32) - Used in conjunction with VID0:VID4 and AF_EN pins to program the diode-emulation and audio filter behavior. Refer to Table 2. BOTTOM - Connects to substrate. Electrically isolated but should be connected to VSS. Requires best practical thermal coupling to PCB.
8
FN6745.1 July 8, 2010
ISL6263C Theory of Operation
The R3 Modulator
The heart of the ISL6263C is Intersil's Robust-RippleRegulator (R3) TechnologyTM. The R3 modulator is a hybrid of fixed frequency PWM control, and variable frequency hysteretic control that will simultaneously affect the PWM switching frequency and PWM duty cycle in response to input voltage and output load transients. The term "Ripple" in the name "Robust-Ripple-Regulator" refers to the synthesized voltage-ripple signal VR that appears across the internal ripple-capacitor CR. The V R signal is a representation of the output inductor ripple current. Transconductance amplifiers measuring the input voltage of the converter and the output set-point voltage VSOFT, together produce the voltage-ripple signal VR. A voltage window signal V W is created across the VW and COMP pins by sourcing a current proportional to gmVSOFT through a parallel network consisting of resistor RFSET and capacitor CFSET. The synthesized voltage-ripple signal VR along with similar companion signals are converted into PWM pulses. The PWM frequency is proportional to the difference in amplitude between V W and VCOMP. Operating on these large-amplitude, low noise synthesized signals allows the ISL6263C to achieve lower output ripple and lower phase jitter than either conventional hysteretic or fixed frequency PWM controllers. Unlike conventional hysteretic converters, the ISL6263C has an error amplifier that allows the controller to maintain tight voltage regulation accuracy throughout the VID range from 0.41200V to 1.28750V.
GPU MODE TABLE 1. VID AND DAC TRUTH TABLE VID4 0 0 0 0 0 0 0 GPU MODE 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 GPU MODE 2 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VSOFT (DAC) (V) 0 1.28750 1.26175 1.23600 1.21025 1.18450 1.15875 1.13300 1.10725 1.08150 1.05575 1.03000 1.00425 0.97850 0.95275 0.92700 0.90125 0.87550 0.84975 0.82400 0.79825 0.77250 0.74675 0.72100 0.69525 0.66950 0.64375 0.61800 0.59225 0.56650 0.54075 0.51500 0.41200
Voltage Programming
The output voltage VOUT is regulated to the SOFT pin voltage, VSOFT, which is determined by the DAC output. The DAC output voltage is programmed by the external five VID pins. Refer to Table 1 for the VID voltage programming specification.
Power-On Reset
The ISL6263C is disabled until the voltage at the VDD pin has increased above the rising VDD power-on reset (POR) VDD_THR threshold voltage. The controller will become disabled when the voltage at the VDD pin decreases below the falling POR VDD_THF threshold voltage.
Start-Up Timing
Figure 4 shows the ISL6263C start-up timing. Once VDD has ramped above VDD_THR, the controller can be enabled by pulling the VR_ON pin voltage above the input-high threshold VVR_ONH. Approximately 100s later, the soft-start capacitor CSOFT begins slewing to the designated VID set-point as it is charged by the soft-start current source ISS. The VOUT output voltage of the converter follows the VSOFT voltage ramp to within 10% of the VID set-point then counts
13 switching cycles, then changes the open-drain output of the PGOOD pin to high impedance. During soft-start, the regulator always operates in continuous conduction mode (CCM).
9
FN6745.1 July 8, 2010
ISL6263C
VDD 10A - OCP + + Isense - PHASE RS COUT LOUT ROCSET
DCR
OCSET ISP
+ -
ICOMP RIS2 CN VO CIS
RNTCS
ISN
ESR
RIS1
RNTC
Rp
+ - VDIFF
VSEN RTN
CFILTER1
RFILTER1 RFILTER2
ROPN1
VOUT VGND ROPN2
TO PROCESSOR KELVIN CONNECTIONS
CFILTER2
CFILTER3
FIGURE 5. SIMPLIFIED GPU KELVIN SENSE AND INDUCTOR DCR CURRENT SENSE
VR_ON
90% ~100s VSOFT/VOUT
ICOMP pin minus the output voltage measured at the VO pin, is proportional to the total inductor current. This information is used for overcurrent protection and current monitoring. It is important to note that this current measurement should not be confused with the synthetic current ripple information created within the R3 modulator. When using inductor DCR current sense, an NTC compensation network is optional to compensate the positive temperature coefficient of the copper winding, thus maintaining the current sense accuracy.
PGOOD
13 SWITCHING CYCLES
Processor Kelvin Voltage Sense
The remote voltage sense input pins VSEN and RTN of the ISL6263C are to be terminated at the die of the GPU. Kelvin sense allows the voltage regulator to tightly control the processor voltage at the die, compensating for various resistive voltage drops in the power delivery path. Since the voltage feedback is sensed at the processor die, removing the GPU will open the voltage feedback path of the regulator, causing the output voltage to rise towards VIN. The ISL6263C will shut down when the voltage between the VO and VSS pins exceeds the severe overvoltage protection threshold VOVPS of 1.55V. To prevent this issue from occurring, it is recommended to install resistors ROPN1 and ROPN2, as shown in Figure 5. These resistors provide voltage feedback from the regulator local output in the absence of the GPU. These resistors should be in the range of 20 to 100.
FIGURE 4. ISL6263C START-UP TIMING
Static Regulation
The output voltage VOUT will be regulated to the value set by the VID inputs per Table 1. A true differential amplifier connected to the VSEN and RTN pins implements processor Kelvin sense for precise core voltage regulation at the GPU voltage sense points. The ISL6263C can accommodate DCR current sense or discrete resistor current sense. The DCR current sense uses the intrinsic series resistance of the output inductor, as shown in the application circuit of Figure 2. The discrete resistor current sense uses a shunt resistor in series with the output inductor, as shown in the application circuit in Figure 3. In both cases, the signal is fed to the non-inverting input of the current sense amplifier at the ISP pin, where it is measured differentially with respect to the output voltage of the converter at the VO pin and amplified. The voltage at the 10
FN6745.1 July 8, 2010
ISL6263C
High Efficiency Diode Emulation Mode
The ISL6263C operates in continuous-conduction-mode (CCM) during heavy load for minimum conduction loss by forcing the low-side MOSFET to operate as a synchronous rectifier. An improvement in light-load efficiency is achieved by allowing the converter to operate in diode-emulation mode (DEM) where the low-side MOSFET behaves as a smart-diode, forcing the device to block negative inductor current flow. Positive-going inductor current flows from either the source of the high-side MOSFET, or the drain of the low-side MOSFET. Negative-going inductor current flows into the source of the high-side MOSFET, or into the drain of the low-side MOSFET. When the low-side MOSFET conducts positive inductor current, the phase voltage will be negative with respect to the VSS pin. Conversely, when the low-side MOSFET conducts negative inductor current, the phase voltage will be positive with respect to the VSS pin. Negative inductor current occurs when the output DC load current is less than 1/2 the inductor ripple current. Sinking negative inductor current through the low-side MOSFET lowers efficiency through unnecessary conduction losses. Efficiency can be further improved with a reduction of unnecessary switching losses by reducing the PWM frequency. The PWM frequency can be configured to automatically make a step-reduction upon entering DEM by forcing a step-increase of the window voltage V W. The window voltage can be configured to increase approximately 30%, 50%, or not at all. The characteristic PWM frequency reduction, coincident with decreasing load, is accelerated by the step-increase of the window voltage. The converter will enter DEM after detecting three consecutive PWM pulses with negative inductor current. The negative inductor current is detected during the time that the high-side MOSFET gate driver output UGATE is low, with the exception of a brief blanking period. The voltage between the PHASE pin and VSS pin is monitored by a comparator that latches upon detection of positive phase voltage. The converter will return to CCM after detecting three consecutive PWM pulses with positive inductor current. The inductor current is considered positive if the phase comparator has not been latched while UGATE is low. Because the switching frequency in DEM is a function of load current, very light load condition can produce frequencies well into the audio band. To eliminate this audible noise, an audio filter can be enabled that briefly turns on the low-side MOSFET gate driver LGATE approximately every 35s. The DEM and audio filter operation are programmed by the AF_EN and FDE pins in conjunction with VID0:VID4 according to Table 2.
TABLE 2. DIODE EMULATION MODE and AUDIO FILTER GPU MODE (VID code) MODE 1 FDE AF_EN
0 1 0 1 1
DEM STATUS DISABLED ENABLED ENABLED ENABLED ENABLED
VOLTAGE WINDOW
NOM 130% NOM 150% NOM 130% NOM 130% NOM
AUDIO FILTER
ENABLED
MODE 2
1 0
Smooth mode transitions are facilitated by the R3 modulator, which correctly maintains the internally synthesized ripple current information throughout mode transitions.
Current Monitor
The ISL6263C features a current monitor output. The voltage between the IMON and VSS pins is proportional to the output inductor current. The output inductor current is proportional to the voltage between the ICOMP and VO pins. The IMON pin has source and sink capability for close tracking of transient current events. The current monitor output is expressed in Equation 1:
V IMON = ( V ICOMP - V O ) 31 (EQ. 1)
Protection
The ISL6263C provides overcurrent protection (OCP), overvoltage protection (OVP), and undervoltage protection (UVP), as shown in Table 3. Overcurrent protection is tied to the current sense amplifier. Given the overcurrent set point IOC, the maximum voltage at ICOMP pin VICOMP(max) (which is the voltage when OCP happens) can be determined by the current sense network (explained in "Inductor DCR Current Sense" on page 14 and "Resistor Current Sense" on page 15). During start-up, the ICOMP pin must fall 25mV below the OCSET pin to reset the overcurrent comparator, which requires (VICOMP(max) - VO) > 25mV. The OCP threshold detector is checked every 15s and will increment a counter if the OCP threshold is exceeded, conversely the counter will be decremented if the load current is below the OCP threshold. The counter will latch an OCP fault when the counter reaches eight. The fastest OCP response for overcurrent levels that are no more than 2.5 times the OCP threshold is 120s, which is eight counts at 15s each. The ISL6263C protects against hard shorts by latching an OCP fault within 2s for overcurrent levels exceeding 2.5 times the OCP threshold. The overcurrent threshold is determined by the resistor ROCSET between OCSET pin and VO pin. The value of ROCSET is calculated in Equation 2:
V ICOMP ( max ) - V O R OCSET = --------------------------------------------------10A (EQ. 2)
11
FN6745.1 July 8, 2010
ISL6263C
For example, choose VICOMP(max) - VO = 80mV. ROCSET can use a 8.06k resistor, according to Equation 2. UVP and OVP are independent of the OCP. If the output voltage measured on the VO pin is less than +300mV below the voltage on the SOFT pin for longer than 1ms, the controller will latch a UVP fault. If the output voltage measured on the VO pin is >195mV above the voltage on the SOFT pin for longer than 1ms, the controller will latch an OVP fault. Keep in mind that VSOFT will equal the voltage level commanded by the VID states only after the soft-start capacitor CSOFT has slewed to the VID DAC output voltage. The UVP and OVP detection circuits act on static and dynamic VSOFT voltage. When an OCP, OVP, or UVP fault has been latched, PGOOD becomes a low impedance and the gate driver outputs UGATE and LGATE are pulled low. The energy stored in the inductor is dissipated as current flows through the low-side MOSFET body diode. The controller will remain latched in the fault state until the VR_ON pin has been pulled below the falling VR_ON threshold voltage VVR_ONL or until VDD has gone below the falling POR threshold voltage VVDD_THF. A severe-overvoltage protection fault occurs immediately after the voltage between the VO and VSS pins exceed the rising severe-overvoltage threshold VOVPS which is 1.545V, the same reference voltage used by the VID DAC. The ISL6263C will latch UGATE and PGOOD low but unlike other protective faults, LGATE remains high until the voltage between VO and VSS falls below approximately 0.77V, at which time LGATE is pulled low. The LGATE pin will continue to switch high and low at 1.545V and 0.77V until VDD has gone below the falling POR threshold voltage VVDD_THF. This provides maximum protection against a shorted high-side MOSFET while preventing the output voltage from ringing below ground. The severe-overvoltage fault circuit can be triggered after another fault has already been latched.
TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263C FAULT DURATION PRIOR TO PROTECTION 120s TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263C (Continued) FAULT DURATION PRIOR TO PROTECTION Immediately
FAULT TYPE Severe Overvoltage (+1.55V) between VO pin and VSS pin
PROTECTION ACTIONS
FAULT RESET
Cycle UGATE, and PGOOD latched low, VDD only LGATE toggles ON when VO > 1.55V OFF when VO < 0.77V until fault reset LGATE, UGATE, and Cycle PGOOD latched low VR_ON or VDD
Undervoltage (-300mV) between VO pin and SOFT pin
1ms
Gate-Driver Outputs LGATE and UGATE
The ISL6263C has internal high-side and low-side N-Channel MOSFET gate-drivers. The LGATE driver is optimized for low duty-cycle applications where the low-side MOSFET conduction losses are dominant. The LGATE pull-down resistance is very low in order to clamp the gate-source voltage of the MOSFET below the VGS(th) at turn-off. The current transient through the low-side gate at turn-off can be considerable due to the characteristic large switching charge of a low rDS(ON) MOSFET.
PWM
LGATE 1V
UGATE 1V
t PDRU
t PDRL
FAULT TYPE Overcurrent
PROTECTION ACTIONS
FAULT RESET
FIGURE 6. GATE DRIVER TIMING DIAGRAM
LGATE, UGATE, and Cycle PGOOD latched low VR_ON or VDD LGATE, UGATE, and Cycle PGOOD latched low VR_ON or VDD LGATE, UGATE, and Cycle PGOOD latched low VR_ON or VDD
Short Circuit
<2s
Overvoltage (+195mV) between VO pin and SOFT pin
1ms
Adaptive shoot-through protection prevents the gate-driver outputs from going high until the opposite gate-driver output has fallen below approximately 1V. The UGATE turn-on propagation delay tPDRU and LGATE turn-on propagation delay tPDRL are found in the "Electrical Specifications" table on page 6. The power for the LGATE gate-driver is sourced directly from the PVCC pin. The power for the UGATE gate-driver is sourced from a boot-strap capacitor connected across the BOOT and PHASE pins. The boot capacitor is charged from PVCC through an internal boot-strap diode each time the low-side MOSFET turns on, pulling the PHASE pin low.
12
FN6745.1 July 8, 2010
ISL6263C
Internal Bootstrap Diode
The ISL6263C has an integrated boot-strap Schottky diode connected from the PVCC pin to the BOOT pin. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit.
2.0 1.8 1.6 CBOOT_CAP (F) 1.4 1.2 1.0 0.8 0.6
nC 50
output voltage is commanded to rise, and discharging CSOFT when the output voltage is commanded to fall. The GPU voltage regulator may require a minimum voltage slew rate, which will be guaranteed by the value of CSOFT. For example, if the regulator requires 10mV/s slew rate, the value of CSOFT can be calculated using Equation 4:
I DVIDmin 180A C SOFT = ------------------------ = ----------------- = 0.018F 10K 10mV --------------- s
(EQ. 4)
QGATE = 100nC
0.4 0.2 20nC
0.0 0.0
I DVID is the soft-dynamic VID current source, and its minimum value is specified in the "Electrical Specifications" table on page 5. Choosing the next lower standard component value of 0.015F will guarantee 10mV/s slew rate. This choice of CSOFT controls the startup slew-rate as well. One should expect the output voltage during soft-start to slew to the voltage commanded by the VID settings at a nominal rate given by Equation 5:
0.5 0.6 0.7 0.8 0.9 1.0
0.1
0.2
0.3
0.4
VBOOT_CAP (V)
I SS dV SOFT 42A 2.8mV ---------------------- = ------------------ = ---------------------- ----------------dt C SOFT 0.015F s
(EQ. 5)
FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
The minimum value of the bootstrap capacitor can be calculated using Equation 3:
Q GATE C BOOT ----------------------V BOOT (EQ. 3)
Note that the slew rate is the average rate of change between the initial and final voltage values. It is worth it to mention that the surge current charges the output capacitors when the output voltage is commanded to rise. This surge current could be high enough to trigger the OC protection circuit if the voltage slew rate is too high, or/and the output capacitance is too large. The overcurrent set point should guarantee the VID code transition successful.
where QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET. The VBOOT term is defined as the allowable droop in the rail of the upper drive. As an example, suppose an upper MOSFET has a gate charge, QGATE , of 25nC at 5V and also assume the droop in the drive voltage at the end of a PWM cycle is 200mV. One will find that a bootstrap capacitance of at least 0.125F is required. The next larger standard value capacitance is 0.15F. A good quality ceramic capacitor is recommended.
RBIAS Current Reference
The RBIAS pin is internally connected to a 1.545V reference through a 3k resistance. A bias current is established by connecting a 1% tolerance, 150k resistor between the RBIAS and VSS pins. This bias current is mirrored, creating the reference current I OCSET that is sourced from the OCSET pin. Do not connect any other components to this pin, as they will have a negative impact on the performance of the IC.
Soft-Start and Soft Dynamic VID Slew Rates
The output voltage of the converter tracks VSOFT, the voltage across the SOFT and VSS pins. Shown in Figure 1, the SOFT pin is connected to the output of the VID DAC through the unidirectional soft-start current source ISS or the bidirectional soft-dynamic VID current source IDVID, and the non-inverting input of the error amplifier. Current is sourced from the SOFT pin when ISS is active. The SOFT pin can both source and sink current when IDVID is active. The soft-start capacitor CSOFT changes voltage at a rate proportional to ISS or IDVID. The ISL6263C automatically selects ISS for the soft-start sequence so that the inrush current through the output capacitors is maintained below the OCP threshold. Once soft-start has completed, IDVID is automatically selected for output voltage changes commanded by the VID inputs, charging CSOFT when the
Setting the PWM Switching Frequency
The R3 modulator scheme is not a fixed-frequency architecture, lacking a fixed-frequency clock signal to produce PWM. The switching frequency increases during the application of a load to improve transient performance. The static PWM frequency varies slightly depending on the input voltage, output voltage, and output current, but this variation is normally less than 10% in continuous conduction mode. Refer to Figure 2 and find that resistor R FSET is connected between the V W and COMP pins. A current is sourced from VW through RFSET creating the synthetic ripple window voltage signal V W, which determines the PWM switching frequency. The relationship between the resistance of RFSET
13
FN6745.1 July 8, 2010
ISL6263C
VDD 10A - OCP + ISENSE - +
OCSET ISP ISN ICOMP
ROCSET RS
+ -
+ RIS2 CN RN VO VN VDCR
FIGURE 8. EQUIVALENT MODEL OF CURRENT SENSE USING INDUCTOR DCR CURRENT SENSE
and the switching frequency in CCM is approximated using Equation 6:
( t - 0.5 x 10 ) R FSET = --------------------------------------- 12 400 x 10
-6
RIS1
(EQ. 6)
Sensing the time varying inductor current accurately requires that the parallel R-C network time constant match the inductor L/DCR time constant. Equation 10 shows this relationship:
RN ( T ) RS L ------------- = ------------------------------- C N DCR R N ( T ) + R S
t is the switching period. For example, the value of RFSET for 300kHz operation is approximated using Equation 7:
( 3.33 x 10 - 0.5 x 10 ) 3 7.1 x10 = -------------------------------------------------------------------- 12 400 x 10
-6 -6
(EQ. 10)
(EQ. 7)
Solution of CN yields:
L ------------- DCR C N = ----------------------------------- RN ( T ) RS ------------------------------ R N ( T ) + R S (EQ. 11)
This relationship only applies to operation in constant conduction mode because the PWM frequency naturally decreases as the load decreases while in diode emulation mode.
Inductor DCR Current Sense
ISL6263C provides the option of using the inductor DCR for current sense. To maintain the current sense accuracy, an NTC compensation network is optional when using DCR sense. The process to compensate the DCR resistance variation takes several iterative steps. Figure 2 shows the DCR sense method. Figure 8 shows the simplified model of the current sense circuitry. The inductor DC current IO generates a DC voltage drop on the inductor DCR. Equation 8 gives this relationship:
V DCR = I O DCR (EQ. 8)
The first step is to adjust RN(T) and RS such that the correct current information appears between the ISP and VO pins even at light loads. Assume VN is the voltage drop across RN(T). The VN to VDCR gain G1(T) provides a reasonable amount of light load signal from which to derive the current information. G1(T) is given by Equation 12:
RN ( T ) G 1 ( T ) = ------------------------------RN ( T ) + RS (EQ. 12)
The gain of the current sense amplifier circuit is expressed in Equation 13:
R IS2 K ISENSE = 1 + -----------R IS1 (EQ. 13)
An R-C network senses the voltage across the inductor to get the inductor current information. RN represents the equivalent resistance of RP and the optional NTC network consisting of RNTC and RNTCS. RN is temperature T dependent and is given by Equation 9:
( R NTC + R NTCS ) R P R N ( T ) = ----------------------------------------------------------R NTC + R NTCS + R P (EQ. 9)
The current sense amplifier output voltage is given by Equation 14:
V ICOMP = V O + V N K ISENSE (EQ. 14)
The inductor DCR is a function of temperature T and is approximated using Equation 15:
DCR ( T ) = DCR ( +25C ) ( 1 + 0.00393 T - ( +25C ) ) (EQ. 15)
If the NTC network is not used, simply set RN(T) = RP.
14
FN6745.1 July 8, 2010
ISL6263C
VDD 10A - OCP + ISENSE - +
OCSET ISP ISN ICOMP
ROCSET RS
+ -
+ RIS2 CN VO VN RP (OPTIONAL) VRSNS
FIGURE 9. EQUIVALENT MODEL OF CURRENT SENSE USING DISCRETE RESISTOR CURRENT SENSE
RIS1
0.00393 is the temperature coefficient of the copper. To make VICOMP independent of the inductor temperature, the NTC characteristic is desired to satisfy:
G 1 ( T ) ( 1 + 0.00393 T - ( +25C ) ) G 1t arg et (EQ. 16)
where G1target is the desired ratio of VN / VDCR. Therefore, the temperature characteristics G1, which determines parameters selection, is described by Equation 17:
G 1t arg et G 1 ( T ) = -----------------------------------------------------------------------1 + 0.00393 ( T - ( +25C ) ) (EQ. 17)
sense. It is recommended to start out using 100 for RS and 47pF for CN. Since the current sense resistance changes very little with temperature, the NTC network is not needed for thermal compensation. Discrete resistor sense design follows the same approach as DCR sense. The voltage on the current sense resistor is given by Equation 19:
V RSNS = I O R SNS (EQ. 19)
It is optional to parallel a resistor RP to form a voltage divider with RS to obtain more flexibility. Assume the voltage across RP is VN, which is given by Equation 20:
RP V N = V RSNS --------------------RS + R
P
It is recommended to begin the DCR current sense design using the RNTC, RNTCS, and RP component values of the evaluation board available from Intersil. Given the inductor DCR and the overcurrent set point IOC, the maximum voltage of ICOMP pin is determined by Equation 18:
R N ( +25C ) R IS2 V ICOMP ( max ) - V O = I OC DCR ( 25C ) --------------------------------------------- 1 + ------------ R IS1 R N ( +25C ) + R S (EQ. 18)
(EQ. 20)
The current sense amplifier output voltage VICOMP is given by Equation 21:
R IS2 V ICOMP = V O + V 1 + ------------ N R IS1 (EQ. 21)
Given an current sense resistor RSNS and the overcurrent set point IOC, the maximum voltage of ICOMP pin is determined by Equation 22:
R IS2 RP V ICOMP ( max ) - V O = I OC R SNS --------------------- 1 + ------------ (EQ. 22) RS + RP R IS1
RN, RS, RIS1, RIS2 should be adjusted to meet the requirement (VICOMP(max) - VO) > 25mV and the time constant matching according to Equation 10. The effectiveness of the RN network is sensitive to the coupling coefficient between the NTC thermistor and the inductor. The NTC thermistor should be placed in the closet proximity of the inductor.
If RP is not used, the maximum voltage of ICOMP pin is determined by Equation 23:
R IS2 V ICOMP ( max ) - V O = I OC R SNS 1 + ------------ R IS1 (EQ. 23)
Resistor Current Sense
Figure 3 shows a detailed schematic using discrete resistor sense of the inductor current. Figure 9 shows the equivalent circuit. Since the current sense resistor voltage represents the actual inductor current information, RS and CN simply provide noise filtering. A low ESL sense resistor is strongly recommended for RSNS because this parameter is the most significant source of noise that affects discrete resistor 15
RS, RP, RIS1, RIS2 should be adjusted to meet the requirement (VICOMP(max) - VO) > 25mV. The current sense traces should be routed directly to the current sense resistor pads for accurate measurement. However, due to layout imperfection, the calculated RIS2 may still need slight adjustment to achieve optimum load line slope. It is recommended to adjust RIS2 after the system has achieved thermal equilibrium at full load.
FN6745.1 July 8, 2010
ISL6263C
Dynamic Mode of Operation - Compensation Parameters
Intersil provides a spreadsheet to calculate the compensator parameters. Caution needs to be used in choosing the input resistor to the FB pin. Excessively high resistance will cause an error to the output voltage regulation due to the bias current flowing through the FB pin. It is recommended to keep this resistor below 3k.
UGATE, BOOT, and PHASE
PHASE is the return path for the entire UGATE high-side MOSFET gate driver. The layout for these signals require similar treatment, but to a greater extent, than those for LGATE, PVCC, and PGND. These signals swing from approximately VIN to VSS and are more likely to couple into other signals.
VSEN and RTN
These traces should be laid out as noise sensitive. For optimum load line regulation performance, the traces connecting these two pins to the Kelvin sense leads of the processor should be laid out away from rapidly rising voltage nodes, (switching nodes) and other noisy traces. The filter capacitors CFILTER1, CFILTER2, and CFILTER3 used in conjunction with filter resistors RFILTER1 and RFILTER2 form common mode and differential mode filters, as shown in Figure 8. The noise environment of the application and actual board layout conditions will drive the extent of filter complexity. The maximum recommended resistance for RFILTER1 and RFILTER2 is approximately 10 to avoid interaction with the 50k input resistance of the remote sense differential amplifier. The physical location of these resistors is not as critical as the filter capacitors. Typical capacitance values for CFILTER1, CFILTER2, and CFILTER3 range between 330pF to 1000pF and should be placed near the IC.
Layout Considerations
As a general rule, power should be on the bottom layer of the PCB and weak analog or logic signals are on the top layer of the PCB. The ground-plane layer should be adjacent to the top layer to provide shielding.
Inductor Current Sense and the NTC Placement
It is crucial that the inductor current be sensed directly at the PCB pads of the sense element, be it DCR sensed or discrete resistor sensed. The effect of the NTC on the inductor DCR thermal drift is directly proportional to its thermal coupling with the inductor and thus, the physical proximity to it.
Signal Ground and Power Ground
The ground plane layer should have a single point connection to the analog ground at the VSS pin. The VSS island should be located under the IC package along with the weak analog traces and components. The paddle on the bottom of the ISL6263C QFN package is not electrically connected to the IC, however, it is recommended to make a good thermal connection to the VSS island using several vias. Connect the input capacitors, the output capacitors, and the source of the lower MOSFETs to the power ground plane.
RBIAS
The resistor RRBIAS should be placed in close proximity to the ISL6263C using a noise-free current return path to the VSS pin.
LGATE, PVCC, and PGND
PGND is the return path for the pull-down of the LGATE low-side MOSFET gate driver. Ideally, PGND should be connected to the source of the low-side MOSFET with a low-resistance, low-inductance path. The LGATE trace should be routed in parallel with the trace from the PGND pin. These two traces should be short, wide, and away from other traces because of the high peak current and extremely fast dv/dt. PVCC should be decoupled to PGND with a ceramic capacitor physically located as close as practical to the IC pins.
VIAS TO GROUND PLANE GND OUTPUT CAPACITORS VOUT INDUCTOR HIGH-SIDE MOSFETS VIN PHASE NODE SCHOTTKY DIODE LOW-SIDE MOSFETS INPUT CAPACITORS
IMON, SOFT, OCSET, V W, COMP, FB, VDIFF, ICOMP, ISP, ISN and VO
The traces and components associated with these pins require close proximity to the IC as well as close proximity to each other. This section of the converter circuit needs to be located above the island of analog ground with the single-point connection to the VSS pin.
Resistor RS
Resistor RS is preferably located near the boundary between the power ground and the island of analog ground connected to the VSS pin.
VID<0:4>, AF_EN, PGOOD, and VR_ON
These are logic signals that do not require special attention.
FDE
This logic signal should be treated as noise sensitive and should be routed away from rapidly rising voltage nodes, (switching nodes) and other noisy traces.
FIGURE 10. TYPICAL POWER COMPONENT PLACEMENT
VIN
The VIN signal should be connected near the drain of the high-side MOSFET.
16
FN6745.1 July 8, 2010
ISL6263C
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. It is best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application. An MLCC should be connected directly across the drain of the high-side MOSFET and the source of the low-side MOSFET to suppress turn-off voltage spikes.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 17
FN6745.1 July 8, 2010
ISL6263C
Package Outline Drawing
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 02/07
4X 3.5 5.00 A B 6 PIN 1 INDEX AREA 28X 0.50 6 PIN #1 INDEX AREA
25 24
32 1
5.00
3 .10 0 . 15
17
(4X) 0.15 16 9
8
0.10 M C A B 4 32X 0.23 - 0.05
+ 0.07
32X 0.40 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0.1
C
BASE PLANE
SEATING PLANE 0.08 C
( 4. 80 TYP ) ( 3. 10 )
( 28X 0 . 5 )
SIDE VIEW
(32X 0 . 23 )
C ( 32X 0 . 60)
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
18
FN6745.1 July 8, 2010

▲Up To Search▲

Price & Availability of ISL6263C

	To Download ISL6263C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .